
\section{3D Cost Model}\label{sec:cost-model}

% JL: We will extend the discussion on prior art in a longer version, for example,
% (1) Yield and Cost Modeling for 3D Chip stack Technologies, P. Mercier et al., IEEE CICC 2006.
% (2) Extending Systems-on-Chip to the Third Dimension: Performance, Cost and Technological Tradeoffs, Roshan Weerasekera et al.
% (3) Temperature- and Cost-Aware Design of 3D Multiprocessor Architecture. Ayse K. Coskun et al.
% (4) Mapping System-on-Chip Designs from 2-D to 3-D ICs, Christianto C. Liu et al.
% (5) Chipsburger: From IP/Design Reuse for SOCs to Manufacture Reuse for 3D ICs. Youn-Long Steve Lin, D43D Workshop 2009.

% JL: Question.  What is the difference between Xiangyu's work and those above?  For one thing, they all appear to use Donath's model for average interconnect length, Rent's rule for logic counts, etc etc..

%In this section, we review the cost model
%from~\cite{dong:aspdac09}, which focuses on manufacture cost, and
%also describe our enhancements.

In 3D integration, the manufacturing cost reduction may come from smaller die area
of each layer as well as reduced number of metals for
routing. The number of metals is predicted by a 3D routability
model, which is based on the wire length
distribution~\cite{dong:aspdac09}. As described
in~\cite{dong:aspdac09}, when a large 2D chip is partitioned into
multiple smaller dies in 3D, the cost could be reduced due to fewer
number of metal layers needed for each smaller die although extra
bonding cost is needed in 3D stacking.

Our cost model is based on a few prior art, particularly the one by Dong et
al.~\cite{dong:aspdac09} with several improvements: (1) It models the number of TSVs for %clock distribution and
power delivery; (2) It differentiates cost models for different
layers (logic/cache/interconnect); 3) It adds mask cost, design
cost, addresses (product) volume factor of each layer, and addresses
(production) time factor of each layer.

It is important to estimate the number of TSVs and its impact on the
die area in 3D stacking since the area overhead caused by TSVs could
be significant depending on the TSV pitch and the design. The TSVs
modeled in~\cite{dong:aspdac09} includes only signal TSVs while the
TSVs used for power delivery %and clock distribution
is not considered.  However, for example, the power grid
distribution via TSVs in 3D is important to leverage on-chip power
density. %Together with clock TSVs, they affect 3D design in addition
%to signal TSVs.
Therefore, we take into account the TSVs for power delivery. % and clock distribution.



%To estimate the number of TSVs for power delivery we
%simplify the model based on the current carried from power to
%ground:
%$$N_{tsvp}=2*P/(I_{tsv}*V)$$
%where $N_{tsvp}$ is the minimum number of TSVs needed for power
%delivery, $P$ is the total power consumption, $V$ is the power
%supply voltage, and $I_{tsv}$ is the current one single TSV can
%carry. This estimation gives the minimum number of TSVs needed in
%order to carry the total current from one layer to another layer. We
%could obtain the valued of $P$ from the design and $I_{tsv}$ from
%TSV size.

The estimation on the number of TSVs for power delivery is based on
voltage drop caused by TSVs. Assume the allowed maximum voltage drop
is $d\%$ and the resistance of one single TSV is $R_{tsv}$, the
number of TSVs is estimated by
$$N_{tsvp}=R_{tsv}/(d\%*V/(P/V))=R_{tsv}*P/0.01*d*V^2$$
where $N_{tsvp}$ is the minimum number of TSVs needed for power
delivery, $P$ is the total power consumption, $V$ is the power
supply voltage. Based on the power and the voltage, the total
resistance caused by TSVs can be estimated. Since all the resistance
of TSVs are connected in parallel, the number of TSVs needed is
obtained from the total resistance and the resistance of one single
TSV. %The design goal of clock distribution is make the clock signal
%to reach flip-flops at the same time so that the clock skew is
%minimized.
%For clock distribution in 3D integration, the complexity is further
%increased compared to 2D since the sequential circuits in the same
%clock domain may be partitioned into different layers. Pavlidis et.
%al designed different clock topologies, such as H-tree, rings and
%meshes for the same design in 3D~\cite{3d-clock}. The number of TSVs
%used for clock distribution really depends on the design itself. For
%example, in the H-tree design, the TSVs are mainly used for
%connecting clock trees in different layers so that the number is
%small enough to be negligible.

In addition to adding TSVs for power, we also distinguish the cost
for different layers such as logic layer (core and interconnect) and
cache layer. The first reason is that cache layer may use fewer
number of metal layers than the logic layer due to its regularity.
Second, different layers may not have the same die area so that it
is necessary to differentiate the cost for each single
layer. %The cost evaluation will be presented in
%Section~\ref{sec:result}.

Another improvement is that we address (product) volume factor of
each layer. In our proposed architecture, the interconnect layer
``ISL'' can be reused in different 3D designs because it is
designed, manufactured and tested as a separate IP component and it
could provide multiple superimposed heterogeneous networks. This
allows ISL to be stacked with different functional units (different
number of cores) and various capacity of storage depending on
different applications/designs to reduce the total cost. After
considering volume, the cost of each die (layer) is defined as
follows~\cite{digital-book}: $C=NRE/Volume + Cost_{die}$, where NRE
stands for non-recurring engineering, including mask and design
cost, $Cost_{die}$ is calculated using the model
from~\cite{dong:aspdac09}, which mainly considers the die cost
including the wafer cost, the wafer yield, the defect density, and
the extra cost caused by 3D bonding. We estimate the design cost and
the mask cost based on~\cite{nre-cost}, in which these two metrics
at different technology nodes are provided. %The design cost includes
%human cost and CAD tools investment, and so on.

The overview of our 3D cost model is shown in
Fig.~\ref{fig:overview}, with our improvements indicated in the
three ovals in the right side. Similar to~\cite{dong:aspdac09}, the
key factor of the die cost model is the die area. We assume that the
wafer cost, the wafer yield, and the defect density are constant for
a specific foundry using a specific technology node. The extra
fabrication steps required by 3D integrations consist of TSV
forming, thinning, and bonding. The entire 3D cost model also
depends on the volume of each single die and some design options,
such as Die-to-Wafer/Wafer-to-Wafer bonding,
Face-to-Face/Face-to-Back bonding, and Known-Good-Die cost in
addition to the wafer cost model and the bonding cost model.

% JL: Xiaoxia - Can you note the other two improvements of the cost model in the following figure, in addition to volume for each die?  Also, why the colors between the boxes?  Does the color assignment has any special meanings?  Either way, let's note our improvements with a different color than the rest and mention it in the figure caption..

\begin{figure}
[htbp] \centering
%\vspace{-8pt}
\includegraphics[width=2.8in]{./figure/overview_cost.eps}
%\vspace{-10pt}
\caption{Overview of the proposed 3D cost model.}
\label{fig:overview} \vspace{-5pt}
\end{figure}
